Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the "Power Wall". Even today, this "Power Wall" is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce "Power-Tokens", to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget.

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